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VLSI Designing Full Course

Module 1: Digital logic Fundamentals and Advanced Digital Design

• Importance and advantages of digital electronics
• Digital Number System, Binary logic gates & Boolean algebra
• Combinational and Sequential circuit designs
• Finite state machine optimization

Module 2: ASIC/FPGA/SOC Design Flow

• What is FPGA? What is ASIC?
• Overview of FPGA/ASIC/SOC design flow
• FPGA Vs ASIC comparison summary
• How to choose between FPGA or ASIC

Module 3: RTL Coding - Verilog HDL

• Introduction to RTL coding
• Overview of digital design with Verilog HDL
• Design modelling with examples
• Tasks and functions
• RTL Simulation and synthesis
• Creating power friendly RTL & Timing analysis
• Module level test bench development
• RTL design optimization techniques

Module 4: Programmable Logic Design

• Read only Memories (ROM)
• PALs & PALs
• CPLDs & FPGAs

Module 5: FPGA Design Example

• FPGA Architecture
• Dual port memory - Example design
• FPGA design Flow
• Bit file generation & downloading the Hex file to FPGA device
• FPGA validation through chipscope & DS5 debugger
• Project work and board bring up

Module 6: Advanced FPGA Concepts

• Overview of 7 series FPGA architecture
• Introduction to Zynq FPGA-SoC --> SoCs with Hardware and Software programmability
• Efficient FPGA RTL coding for design synthesis & Implementation

Module 7: Xilinx Design Implementation tools & Xilinx's Evalution board for Prototyping

• Xilinx tool introduction & Installation
• RTL simulation - Qsim from Mentor graphics
• Hands-on experience in using vivado design suite for design synthesis and Implementation

Module 8: Soft Skill Development

• RTL coding, lint checks
• RTL integration
• Connectivity checks
• Functional Verification
• Synthesis & STA
• Gate level simulations
• Power aware simulations
• Placement and Routing
• DFT
• Custom layout
• Post silicon validation
• Digital Design – Deep dive
• Combinational logic
• Number systems
• Radix conversions
• K-maps, min-terms, max terms
• Logic gates
• Realization of logic gates using mux’s and universal gates
• Compliments (1/2/9/10’s complement)
• Arithmetic operations using compliments
• Boolean expression minimization, Dmorgan theorems
• POS and SOP
• Conversion and realization
• Adders
• Half adder
• Full adder
• Subtractor
• Half subtractor
• Full subtractor
• Multiplexers
• Realizing bigger Mux’s using smaller Mux’s
• Implementing Adders and subtractors using Multiplexers
• Decoders and Encoders
• Implementing Decoders and Encoders using Mux and Demux
• Bigger Decoder/Encoder using smaller Decoder/Encoder
• Comparators
• Implementing multi bit Comparators using 1-bit Comparator
• Sequential logic
• Latch, Flipflop
• Latch, Flipflop using Gates or Mux’s
• Different types of FFs
• FF Truth table
• Excitation tables
• Realization of FF’s using other FF’s
• Applications of FF’s, Latches
• Counters
• Shift registers
• Synchronizers for clock domain crossing
• FSM’s
• Mealy, Moore FSM
• Different encoding styles
• Frequency dividers
• Frequency multiplication
• STA
• Setup time, Hold time, timing closure
• fixing setup time and hold time violations
• Launch flop, capture flop
• SOC Design and Verification concepts
• SOC Architecture overview
• SOC design concepts
• SOC verification concepts
• SOC Components
• SOC use cases
• SOC Testbench architecture
• SOC Test Case coding
• SOC verification differences with moduleverification
• Verilog language – Deep dive
• Verilog language basics
• Verilog: How the language evolved?
• Verilog execution using Modelsim
• Verilog constructs
• Literals
• Data types
• Operators
• Continuous assignments
• Procedural timing controls
• task and functions
• system task and function
• modeling memories and FSM
• Parameters
• Port connections
• Procedural blocks
• Sensitivity list
• State machines
• timescale
• Verilog timing regions
• process
• Blocking and nonblocking statements
• Inferring combinational and Sequential logic
• fork join
• Race conditions
• Synthesis examples
• Inter and Intra delay statements
• Pipelining
• Verilog design and verification projects
• DFF coding using gate level, behavioural
• Counters
• Up counter
• Ring counter
• Johnson counter
• Memory design and verification
• Memory Verilog coding
• Front door access
• Back door access test case coding
• Test case coding and understanding waveforms
• FIFO – Synchronous FIFO and Asynchronous FIFO
• Synchronous FIFO
• Asynchronous FIFO
• Finite state machines
• Mealy and Moore style
• Implicit and Explicit styles of coding.
• Pattern detector – Overlapping, Non-Overlapping, Dynamic
• Overlapping
• Non-Overlapping
• Dynamic
• Traffic light controller
• APB protocol
• Interrupt controller
• SPI controller
• CRC generation
• FPGA Design and FPGA design Flow
• PAL, CPLD and FPGA basics
• FPGA Design Flow
• FPGA Architecture
• Internals of FPGA and CPLD
• Logic implementation
• FPGA Architectures of various FPGA vendors
• Anti-fuse and SRAMS
• Logic elements and Look-up Tables
• Dedicated multipliers
• Distributed RAM
• Shift registers
• MMCM
• Kintex
• Zynq
• Virtex Architectures
• IP Cores
• Introduction and usage of IP cores·
• FPGA Simulation and Synthesis Tool Flow
• Modelsim/Icarus Verilog simulation
• Design Synthesis
• FPGA Implementation Design Flow
• Design constraining and pin locking
• Timing analysis
• slack calculation
• Data loss due to large skew
• Maximum skew calculations with examples
• Period constraints
• Area and Power Constraints
• Static Timing Analysis
• FPGA programming
• Translate
• Map
• Floor plan
• Place and Route
• Post map and Post P&R simulation
• XDC constraints
• Reading and analysing reports-post synthesis
• Post map simulation
• Post P·&R simulation
• Configuring FPGAs
• FSM Extraction
• Timing Simulation and Programming
• Timing Simulation using Modelsim/Icarusverilog
• Programming using JTAG
• System Level testing and debugging
• Debugging techniques
• Debugging using chip scope and Logic analyzers

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VLSI Designing Full Course

Module 1: Digital logic Fundamentals and Advanced Digital Design

Module 2: ASIC/FPGA/SOC Design Flow

Module 3: RTL Coding - Verilog HDL

Module 4: Programmable Logic Design

Module 5: FPGA Design Example

Module 6: Advanced FPGA Concepts

Module 7: Xilinx Design Implementation tools & Xilinx's Evalution board for Prototyping

Module 8: Soft Skill Development

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